1. Field of the Invention
The present invention relates generally to semiconductor devices and a method of manufacturing the same, and more particularly, to a semiconductor device with an improved operation rate and improved element isolation and a method of manufacturing such semiconductor device.
2. Description of the Background Art
In order to execute processing or operation of information in a digital system, memory devices (IC memories) have been recently developed which once store binary-decoded information or data which are read as necessary.
IC memories are classified into several groups according to their functions, one of which is a DRAM (Dynamic Random Access Memory) which stores information according to presence/absence of charges stored in a capacitor, and which is re-written (refreshed) by charging at constant time intervals and loses all its storage when power is off (volatile).
With reference to FIG. 26, the DRAM is basically constituted by a memory cell array 100 including numerous semiconductor memory devices, an X decoder 110 and a Y decoder 120 necessary for inputting/outputting and an input/output control circuit 130.
With reference to FIG. 27, semiconductor memory devices 140 in the memory cell array 100 are disposed at cross-over points between a plurality of word lines WL.sub.1, WL.sub.2, . . . WL.sub.n extending in a row direction and a plurality of bit lines BL.sub.1, BL.sub.2, . . . BL.sub.n extending in a column direction.
Again with reference to FIG. 26, an address signal for designating a position of a target semiconductor device 140 is applied from an X address 110a and a Y address 120a. Writing to and reading of the target semiconductor device 140 is carried out by an input/output control signal 130a. The X decoder 110 and the Y decoder 120 are circuits for selecting an address by using an address signal.
The above-described semiconductor device 140 is a memory for storing information according to presence/absence of charges stored in a capacitor. FIG. 28 shows an equivalent circuit of the semiconductor device 140. The semiconductor device 140 includes one field effect transistor 150 and one capacitor 160. Reading is carried out by determining the presence/absence of charges stored in the capacitor 160 by a current flowing through a capacitance C.sub.D of a precharged bit line to the field effect transistor 150.
FIG. 29 is a plan view of the memory cell array 100. Bit lines 60 are disposed in a column direction to come in contact, at bit line contact portions 59, with impurity diffusion regions 54 provided on a semiconductor substrate 51. Word lines 55 are disposed in a row direction.
With reference to FIG. 30, an internal structure of the semiconductor memory device 140 will be described. FIG. 30 is a sectional view taken along line X--X of FIG. 29.
An element isolation region 52 is formed on a main surface of a p type semiconductor substrate 51. In an active region surrounded by the element isolation region 52, a word line 55 is formed on the main surface of the p type semiconductor substrate 51 through an insulation film 70.
n type impurity regions 53 and 54 are formed from the surface of the p type semiconductor substrate 51 down to a predetermined depth, at a position in which the regions sandwich the above word line 55.
The word line 55 has an upper surface and a side surface covered with an insulation film 71. Formed on the upper surface side of the insulation film 71 is a first semiconductor layer of polysilicon with n type impurities doped along its surface. The first semiconductor layer 57 is electrically connected to the impurity region 53 at a contact hole 71a provided in the insulation film 71.
An insulation film 61 of an oxide film is formed along the surface of the first semiconductor layer 57. A second semiconductor layer 58 of polysilicon with n type impurities doped is formed along the surface of the insulation film 61. Formed on the surface of the second semiconductor layer 58 is an interconnection layer 60 through an interlayer insulation film 59. The interconnection layer 60 is electrically connected to the impurity region 54 at a contact hole 59a provided in the interlayer insulation film 59.
In the semiconductor device 140 having the above-described structure, the word lines 55 and the impurity regions 53 and 54 constitute a field effect transistor. Furthermore, the first semiconductor layer 57 forms a lower electrode, the insulation layer 61 forms a dielectric layer and the second semiconductor layer 58 forms an upper electrode, which together constitute a capacitor.
A method of manufacturing the semiconductor device 140 of the above-described structure will be described in the following with reference to FIGS. 31 to 45.
First with reference to FIG. 31, an element isolation region 52 is formed on a main surface of a p type semiconductor substrate 51 by a LOCOS method. With reference to FIG. 32, an oxide film 70 is formed entirely on the main surface of the semiconductor substrate 51. With reference to FIG. 33, a polysilicon layer 55a is formed on the entire surface of the semiconductor substrate 51. With reference to FIG. 34, a resist film 72 of a predetermined configuration is formed on the surface of the polysilicon layer 55a by photolithography. With reference to FIG. 35, the polysilicon layer 55a and the oxide film 70 are anisotropically etched by using the resist film 72 as a mask to form a word line 55.
Then with reference to FIG. 36, after a removal of the resist film 72, phosphorus is implanted into the main surface of the semiconductor substrate 51 by using the word line 55 and the element isolation region 52 as masks to form n type impurity regions 53 and 54. With reference to FIG. 37, an oxide film 71 is deposited on the entire surface of the semiconductor substrate 51 by the CVD method. With reference to FIG. 38, the oxide film 71 is etched by anisotropic etching, etc. to form a contact hole 71a in communication with the impurity region 53.
Then with reference to FIG. 39, polysilicon including high-concentration phosphorus is deposited along the surfaces of the insulation film 71 and the contact hole 71a to form a first semiconductor layer 57. With reference to FIG. 40, a resist film 21 of a predetermined configuration is formed on the surface of the first semiconductor layer 57 and the first semiconductor layer 57 virtually above the impurity region 54 is removed by anisotropic etching. With reference to FIG. 41, after the removal of the resist film 21, an insulation layer 61 of an oxide film is formed on the entire surface of the first semiconductor layer 57. With reference to FIG. 42, a second semiconductor layer 58 of polysilicon including high-concentration phosphorus is formed on the surfaces of the insulation layer 61 and the oxide film 71.
Then with reference to FIG. 43, a resist film 22 of a predetermined configuration is formed on the surface of the second semiconductor layer 58 and the second semiconductor layer 58 virtually above the impurity region 54 is removed by anisotropic etching. With reference to FIG. 44, after the removal of the resist film 22, an interlayer insulation film 59 is formed on the entire surface of the second semiconductor layer 58. With reference to FIG. 45, after sintering of the interlayer insulation film 59 and planarization of the surface, a contact hole 59a reaching the impurity region 54 is formed by photolithography etc. Thereafter, a semiconductor device 140 as shown in FIG. 30 is completed by forming an interconnection layer 60 of polysilicon or the like on the surface of the interlayer insulation film 59 and in the contact hole 59a.
However, with reference to FIG. 45, the semiconductor device having the above-described structure has its capacitor liable to destruction due to a concentration of an electric field because the capacitor is sharp at the point A encircled by a line. In addition, because of a high impurity concentration of the first semiconductor layer 57, a parasitic capacitance is generated between the word line 55 and the first semiconductor layer 57. As a result, a word line further from a word line drive circuit (not shown) takes more time in a voltage change, thereby lowering an operation rate of the semiconductor device. Similarly, a parasitic capacitance is generated between the interconnection layer 60 and the second semiconductor layer 58 to reduce an operation rate of the semiconductor device.
On the other hand, impurities included in the first semiconductor layer diffuse into an impurity region by a heat treatment step, etc. in manufacturing process, thereby increasing a depth of the diffusion of the impurity region on the surface of a substrate.
Again with reference to FIGS. 41 to 45, it can be seen that the impurity diffusion region is greatly enlarged through the respective steps. In particular, in a heat treatment for planarization of the interlayer insulation film 59, impurities diffuse deep into the substrate even by a gentle heat treatment carried out at about 850.degree. C. for two hours. FIG. 46 shows a profile of an impurity concentration at a section taken along line X--X of FIG. 30. The deeper the impurity region provided in the substrate becomes as described above, the smaller becomes the distance between the impurity region and an impurity region of its adjacent element as shown in FIG. 46. As a result, depletion layers 80 generated at the interface of the impurity diffusion region connect to each other to cause punch through, resulting in deterioration of semiconductor element characteristics and defects of storage.
Means for solving such problems include a method of suppressing impurities from diffusing into an impurity region by decreasing a concentration of impurities included in the first semiconductor layer and a method of lowering a heat treatment temperature for planarization of an interlayer insulation film. According to the diffusion depression method, however, when the impurity concentration of the first semiconductor layer is decreased, a resistance value of interconnection of the first conductor layer is increased to reduce a capacitance of a capacitor. According to the latter method, planarization of the interlayer insulation film is not so sufficient that the surface of the interlayer insulation film is staged, which adversely affects a formation of an interconnection layer etc. in the following steps. Both method consequently lower element characteristics.